Virage Logic and Tensilica Introduce Core-Optimized IP Kits

The new Core-Optimized IP Kits consist of Virage Logic's Area, Speed and Power (ASAP) Memory(TM) and ASAP Logic(TM) IP, and are optimized for each of the Diamond cores to allow designers to target area, performance or power.

"As the industry's trusted IP partner, we're pleased to collaborate with Tensilica to provide our mutual customers with physical IP that is specifically tuned to optimize the performance of Tensilica's Diamond Standard product line processor cores," stated Jim Ensell, senior vice president of marketing and business development at Virage Logic. "By making the Core-Optimized IP Kits available via our website, we're making this solution easily accessible and also helping our customers accelerate their silicon success."

"We've worked with Virage Logic for several years, and they've been an outstanding IP provider for our customers," stated Steve Roddy, Tensilica's vice president of marketing. "Our Xtensa(R) customers have completed many designs with Virage Logic's libraries. Now, with physical IP optimized for our Diamond Standard processors, we expect to provide our mutual customers with a greater competitive advantage."

The Core-Optimized IP Kits target four of Tensilica's Diamond Standard processors, a set of off-the-shelf synthesizable cores that range from area-efficient, low-power controllers to an audio processor and a high-performance DSP, all of which lead the industry in their respective categories both in lowest power and highest performance. The Core-Optimized IP Kits provide access to Virage Logic's silicon proven embedded memory IP and standard cell libraries to meet a variety of market requirements.

By Virage Logic