Available in dual data rate, low-voltage differential signaling (LVDS) and CMOS output options, the ADCs are targeted at demanding and 3G wireless communications applications. In high intermediate frequency (IF) sampling receiver applications, the 1.1 GHz bandwidth capability of these ADCs provides high spurious free dynamic range (SFDR) and signal-to-noise ratio (SNR) performance that extends well beyond 250 MHz input frequencies. This enables the system designer to digitize the signal at the first IF, thereby eliminating a down conversion stage, which reduces component count and system power.
The 12-bit ADC12C170 with parallel CMOS outputs and 12-bit ADC12V170 with dual data rate, parallel LVDS outputs offer the industry’s highest SFDR above 250 MHz input frequencies. Compared to competitive devices, the ADC12C170 at 84.1 dB offers 5.5 dB better SFDR and the ADC12V170 at 83 dB offers 3.8 dB better SFDR at an input frequency of 250 MHz.
At 1.1 GHz, the ADC14V155 delivers 57 percent higher full-power bandwidth than competing 14-bit ADCs. The device also provides an industry-leading SFDR of 85 dB and SNR of 69.5 dB at an input frequency of 238 MHz. The ADC14V155, with dual data rate, parallel LVDS outputs is the latest addition to National’s high-speed 14-bit ADC family, joining the ADC14155, with CMOS outputs, introduced in mid-2006.
These ADCs are well-matched to work with National’s high-speed op amps and highly-integrated clock conditioners, such as the single-chip LMK03000, to provide a complete signal-path system solution.
Key Features – ADC12C170 and ADC12V170
The ADC12C170 and ADC12V170 employ a differential, pipelined architecture and operate in single-ended or differential clock modes. At an input frequency of 70 MHz, the ADC12C170 provides 85.4 dB SFDR and 67.2 dB SNR, while the ADC12V170 provides 85.8 dB SFDR and 67.2 dB SNR. The ADC12C170 operates from a 3.3V supply and typically consumes 715 mW, while the ADC12V170 typically consumes 781 mW. Both ADCs include a power-down feature to reduce power consumption to 5 mW. The combination of high SFDR performance and low power makes them well suited for digital pre-distortion techniques to improve power amplifier efficiency in base station applications. The ADC12C170 and ADC12V170 are supplied in a 48-pin LLP® package and are pin-equivalent to the 14-bit ADC14155 and ADC14V155, respectively.
Key Features – ADC14V155
The ADC14V155 employs a differential, pipelined architecture and operates in single-ended or differential clock mode. Its superior dynamic performance and linearity at high IF allows for the consolidation of signal paths, enabling the migration from a single carrier architecture to a multi-carrier approach where a single ADC digitizes several carriers. The device’s low-jitter front-end allows the digitization of high frequency inputs up to 450 MHz, providing flexibility in system frequency planning. The ADC14V155 operates from a 3.3V supply and typically consumes 951 mW. It offers a power-down feature to reduce power consumption to 15 mW, while a separate 1.8V supply for the digital interface allows low-power operation with reduced noise. The ADC14V155 is supplied in a 48-pin LLP package.-National Semiconductor Corporation
Posted August 20th, 2007 by harminka
